The present invention relates generally to the analysis of integrated circuits (ICs), and, more particularly, to methods for performing statistical static timing analysis on the IC.
Static timing analysis (STA) is a method of computing the expected timing of an IC without circuit simulation. High-performance ICs have traditionally been characterized by clock frequencies at which they operate. Gauging the ability of a circuit to operate at a specified speed requires an ability to measure, during the design process, its delays at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach requires tremendous amount of calculations and would take too long to be practical. Static timing analysis uses simplified delay models to measure circuit timing with reasonable accuracies and in much shorter time. STA has an advantage that it does not require input vectors and has a run time that is linear with the size of the circuit.
Traditionally, process variations have been modeled in STA using so called corner analysis. In this methodology, best-corner, nominal and worst corner SPICE parameters sets are constructed and the timing analysis is performed several times, each time using one corner file. Each execution of STA is therefore deterministic, meaning that the analysis uses deterministic delays for the gates and any statistical variation in the underlying silicon is ignored. While this approach has been successfully used in the past to model die-to-die variations, it is not able to accurately model variations within a single die. With the continual scaling of feature sizes, the ability to control critical device parameters on a single die has become increasingly difficult. Using a worst corner analysis for these variations therefore leads to very pessimistic analysis results since it assumes that all devices on a die have worst corner characteristics, ignoring their inherent statistical variation. The emerging dominance of process variations, therefore, poses a major obstacle for deterministic STA, and gives rise to the need for statistical static timing analysis (SSTA) approaches.
In general, process variations can be divided into inter-die variations and intra-die variations. Inter-die variations are variations that occur from one die to the next, meaning that the same device on a chip has different features among different die of a wafer, from wafer to wafer, and from wafer lot to wafer lot. Intra-die variations are variations in device features that are present within a single chip, meaning that a device feature varies between different locations on the same die. Intra-die variation results from equipment limitations or statistical effects in the fabrication process, such as statistical variations in the doping concentrations.
However, comparing to conventional STA, SSTA needs to characterize more libraries to produce nominal timing entities and their sensitivities with respect to process and environmental parameters. A library is a file containing timing and logical information about a collection of circuit cells. The nominal-and-sensitivity combined timing entities are used to predict distributions of circuit performance while verifying its timing. To be specific, there are three types of libraries for the SSTA. They are nominal, shifted inter-die and shifted intra-die libraries. The shifted inter-die libraries relates to the global process variation. The shifted intra-die libraries relates to the local process variation. More libraries to be characterized will obviously take more time and disk space in the SSTA operation. The time and disk space consumption issue will become more acute when the IC under timing analysis is very large and complicated.
As such, what is desired is a method for performing SSTA on complex ICs with reduced number of libraries needed to be characterized.